One way of mitigating the effects of soft errors in data storage memory structures in microprocessors, such as cache memories, is to use error detection mechanisms such as Error Correcting Codes (“ECC”) to detect and, in some cases, correct soft errors when they occur. Soft errors may occur when high-energy alpha particles strike a memory cell and cause the memory cell to change state to a different value. Because alpha particles are charged particles, the amount of electrical charge stored in a memory cell may change when alpha particles strike the memory cell. If the charge alteration in the memory cell is sufficiently large, the voltage on the memory cell may change from a level that represents one logic state to a level that represents a different logic state, in which case the information stored in that memory cell becomes corrupted. Generally, soft error rates increase as circuit dimensions decrease, because the likelihood that an alpha particle will strike a memory cell increases when the circuit density increases. Moreover, caches are especially vulnerable to soft errors because caches typically span a large area of a microprocessor, and hence increasing the probability that an alpha particle will strike somewhere in the cache of the microprocessor.
An ECC error detection mechanism uses a coding algorithm such as a Hamming code to encode information about a block of memory contents into ECC bits that contain sufficient details about the memory contents to permit recovery of errors in the memory contents. Depending on the specific implementation, the level of detection or correction capability may be limited to one or two bit errors. While the use of ECC error detection mechanism may increase data reliability, it comes at the costs of addition circuitry to compute the ECC bits, additional memory to store the ECC bits, a reduction in performance due to the additional time needed to perform the error detection and/or correction operations, and an increase in power consumption associated with performing the error detection and/or correction operations.